Fujitsu/LSI 16 core SPARC64-IXfx

The register detail the new FJ SPARC64-IXfx chip and PrimeHPC FX10
and cpu-world  provide some detail

SPARC64-IXfx

16 core

• each core : 
• 32KB L1 D$, 32KB L1 I$
• two INT IU
• two address calculaion unit,
• four FP unit FMA  allow fat SIMD span two FP unit (8 flops/core)
• a Storage Unit SU (Ld/Store)
• 12MB L2$
• integrated  memory controller/DDR3
• 64GB
• Bandwidth 86GB/sec
• designed by FJ with LSI
• Fabbed by TSMC @40nm
• 21.9mm x22.1mm
• 110W
• 1.85Ghz@128flops=236 gflops
• 4 Tofu Interconnect interface
• handles collective operations
• Tofu router: 10 Tofu links
• 6D mesh/torus
• PCI_E2 controller
• 65nm@312.5Mhz
• 10 bi-diectional orts@5GB/sec peak of 100GB/sec switching capacity
•  

PRIMEHPC FX10 SW

• 4 SPARC64-IXfs per blade
• 4 Tofu interconnect chips per blade
• cooled with water blocks attached to rear door water jackets
• base PrimeHPC FX10 
• 64 racks@$650k
• 6144 process
• 385TB RAM
• 384 I/O nodes
• 1536 expansion slots
• 1.5 pflops peak
• 1.4 MegaW
• Fujitsu Exabyte File System/variant of Lustre FS
•